From: Christophe Lyon <christophe.lyon@st.com>
Date: Fri, 20 Sep 2019 13:32:20 +0000 (+0200)
Subject: Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76c93295f3b3fec8f34fccbb2c5d574c1362752a;p=gcc.git

Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture

This is causing regressions when mixing with user code compiled in ARM mode.

2019-09-20  Christophe Lyon  <christophe.lyon@st.com>

	Revert:
	2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
		Mickaël Guêné <mickael.guene@st.com>

	* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
	architecture.

From-SVN: r276001
---

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 37fadd4149c..74deb0f185a 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-09-20  Christophe Lyon  <christophe.lyon@st.com>
+
+	Revert:
+	2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
+		Mickaël Guêné <mickael.guene@st.com>
+
+	* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
+	architecture.
+
 2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
 
 	* config/aarch64/lse-init.c: New file.
diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c
index 8313ee03e90..9ba73e72a2a 100644
--- a/libgcc/config/arm/unwind-arm.c
+++ b/libgcc/config/arm/unwind-arm.c
@@ -199,11 +199,6 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context,
 	return _UVRSR_FAILED;
 
       vrs->core.r[regno] = *(_uw *) valuep;
-#if defined(__thumb__)
-      /* Force LSB bit since we always run thumb code.  */
-      if (regno == R_PC)
-	vrs->core.r[regno] |= 1;
-#endif
       return _UVRSR_OK;
 
     case _UVRSC_VFP: