From: lkcl <lkcl@web>
Date: Sun, 11 Sep 2022 00:51:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~508
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76e4a9c7f7a50e3ff0dbd00fcff1da79c45a682f;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 99f1f2302..0c36967d5 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -6,14 +6,14 @@
   [[ls001/discussion]]
 
 This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
-Vectorisation Concept that may be applied to **all and any** suitable
+Vectorisation Concept that may be orthogonally applied to **all and any** suitable
 Scalar instructions, present and future, in the Scalar Power ISA.
 The Vectorisation System is called
 ["Simple-V"](https://libre-soc.org/openpower/sv/)
 and the Prefix Format is called
 ["SVP64"](https://libre-soc.org/openpower/sv/).
 **Simple-V is not a Traditional Vector ISA and therefore
-does not add Vector opcodes**.
+does not add Vector opcodes or regfiles**.
 An ISA Concept similar to Simple-V was originally invented in 1994 by
 Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not
 have an Out-of-Order Microarchitecture on which to best exploit it.