From: Dmitry Selyutin Date: Sun, 28 May 2023 22:04:57 +0000 (+0300) Subject: ppc: support dsld instruction X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76e72ab3ccc068f4fa54c2cc12489f5f90f22dcb;p=binutils-gdb.git ppc: support dsld instruction --- diff --git a/gas/testsuite/gas/ppc/dsld.d b/gas/testsuite/gas/ppc/dsld.d new file mode 100644 index 00000000000..bd39d491934 --- /dev/null +++ b/gas/testsuite/gas/ppc/dsld.d @@ -0,0 +1,16 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*:\s+(13 e0 00 34|34 00 e0 13)\s+dsld\s+r31,r0,r0,r0 +.*:\s+(10 1f 00 34|34 00 1f 10)\s+dsld\s+r0,r31,r0,r0 +.*:\s+(10 00 f8 34|34 f8 00 10)\s+dsld\s+r0,r0,r31,r0 +.*:\s+(10 00 07 f4|f4 07 00 10)\s+dsld\s+r0,r0,r0,r31 +.*:\s+(13 e0 00 35|35 00 e0 13)\s+dsld.\s+r31,r0,r0,r0 +.*:\s+(10 1f 00 35|35 00 1f 10)\s+dsld.\s+r0,r31,r0,r0 +.*:\s+(10 00 f8 35|35 f8 00 10)\s+dsld.\s+r0,r0,r31,r0 +.*:\s+(10 00 07 f5|f5 07 00 10)\s+dsld.\s+r0,r0,r0,r31 diff --git a/gas/testsuite/gas/ppc/dsld.s b/gas/testsuite/gas/ppc/dsld.s new file mode 100644 index 00000000000..4bd8acae3b6 --- /dev/null +++ b/gas/testsuite/gas/ppc/dsld.s @@ -0,0 +1,8 @@ +dsld 31,0,0,0 +dsld 0,31,0,0 +dsld 0,0,31,0 +dsld 0,0,0,31 +dsld. 31,0,0,0 +dsld. 0,31,0,0 +dsld. 0,0,31,0 +dsld. 0,0,0,31 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 6138de6a31a..6f41bb48b35 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -171,3 +171,4 @@ run_dump_test "fptrans" run_dump_test "maddedu" run_dump_test "divmod2du" run_dump_test "sadd" +run_dump_test "dsld" diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index e9f9d3ac971..7f4486a2ae4 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4957,6 +4957,13 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); | (((uint64_t)(xop)) & 0x1f)) #define BM2_MASK BM2 (0x3f, 0x1f) +/* An VA2 form instruction. */ +#define VA2(op, xop, rc) \ + (OP (op) \ + | ((((uint64_t)(xop)) & 0x1f) << 1) \ + | (((uint64_t)(rc)) & 1)) +#define VA2_MASK VA2 (0x3f, 0x1f, 0x1) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -5207,6 +5214,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, +{"dsld", VA2(4,26,0), VA2_MASK, SFFS, PPCVLE, {RT, RA, RB, RC}}, +{"dsld.", VA2(4,26,1), VA2_MASK, SFFS, PPCVLE, {RT, RA, RB, RC}}, {"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, {"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},