From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 21:26:12 +0000 (-0700)
Subject: Really get rid of 'opt_expr -fine' by being explicit
X-Git-Tag: working-ls180~1039^2~150
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76eedee08928f035f00f46304d1b49e9502401c1;p=yosys.git

Really get rid of 'opt_expr -fine' by being explicit
---

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 75b1242a2..51a6c5fb9 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -148,8 +148,17 @@ module _80_mul (A, B, Y);
 				//       reduction' approach also exists...
 				if (i == 0)
 					assign partial_sum[i] = partial[i];
-				else
-					assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
+				else begin
+					// Rewrite the following statement explicitly in order
+					//   to save on a call to 'opt_expr -fine' which would
+					//   optimise away the '<<' op and trim size of adder
+					//assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
+					wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
+					assign partial_sum[i] = {
+						partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
+						shifted_sum[Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]
+					};
+				end
 			end
 
 			\$__mul #(
@@ -163,7 +172,12 @@ module _80_mul (A, B, Y);
 				.B(B),
 				.Y(last_partial)
 			);
-			assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
+			//assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
+			wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
+			assign partial_sum[n] = {
+				partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
+				shifted_sum[Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]
+			};
 			assign Y = partial_sum[n];
 		end
 		else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
@@ -199,8 +213,16 @@ module _80_mul (A, B, Y);
 				//       reduction' approach also exists...
 				if (i == 0)
 					assign partial_sum[i] = partial[i];
-				else
-					assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
+				else begin
+					// Rewrite the following statement explicitly in order
+					//   to save on a call to 'opt_expr -fine' which would
+					//   optimise away the '<<' op and trim size of adder
+					wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
+					assign partial_sum[i] = {
+						partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
+						shifted_sum[Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]
+					};
+				end
 			end
 
 			\$__mul #(
@@ -214,7 +236,12 @@ module _80_mul (A, B, Y);
 				.B(B[B_WIDTH-1 -: last_B_WIDTH]),
 				.Y(last_partial)
 			);
-			assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
+			//assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
+			wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
+			assign partial_sum[n] = {
+				partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
+				shifted_sum[Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]
+			};
 			assign Y = partial_sum[n];
 		end
 		else begin
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 9ad28a933..4ca8a4667 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -325,9 +325,6 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-				// Necessary for optimising away $shl cells, as well as $add cells
-				//   that have inputs with 1'b0 LSBs
-				run("opt_expr -fine", "                 (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}