From: Darrell Harmon <dlharmon@users.noreply.github.com>
Date: Mon, 23 Sep 2019 16:28:15 +0000 (-0600)
Subject: vendor.xilinx_spartan_3_6: override reset synchronizer.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76f99e1ff159a667753830ac71001634914a572e;p=nmigen.git

vendor.xilinx_spartan_3_6: override reset synchronizer.
---

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 0a5df0e..382e3a1 100644
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -419,6 +419,18 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m.d.comb += ff_sync.o.eq(multireg._stages[-1])
         return m
 
+    def get_reset_sync(self, resetsync):
+        m = Module()
+        m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
+        for i, o in zip((0, *resetsync._stages), resetsync._stages):
+            o.attrs["ASYNC_REG"] = "TRUE"
+            m.d.reset_sync += o.eq(i)
+        m.d.comb += [
+            ClockSignal("reset_sync").eq(ClockSignal(resetsync._domain)),
+            ResetSignal("reset_sync").eq(resetsync.arst),
+            ResetSignal(resetsync._domain).eq(resetsync._stages[-1])
+        ]
+        return m
 
 XilinxSpartan3APlatform = XilinxSpartan3Or6Platform
 XilinxSpartan6Platform = XilinxSpartan3Or6Platform