From: Luke Kenneth Casson Leighton Date: Fri, 27 Mar 2020 09:44:30 +0000 (+0000) Subject: Re: [libre-riscv-dev] cache SRAM organisation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7702322c0248cb23d855cc007dbeeadc35e706e1;p=libre-riscv-dev.git Re: [libre-riscv-dev] cache SRAM organisation --- diff --git a/c9/d6e4133c5097a22a02c751318d8032d7201f2c b/c9/d6e4133c5097a22a02c751318d8032d7201f2c new file mode 100644 index 0000000..7175b23 --- /dev/null +++ b/c9/d6e4133c5097a22a02c751318d8032d7201f2c @@ -0,0 +1,128 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 27 Mar 2020 09:45:07 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHlY2-0003Ap-RO; Fri, 27 Mar 2020 09:45:06 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jHlXz-0003Af-8h + for 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