From: lkcl <lkcl@web>
Date: Sun, 24 Jan 2021 00:31:04 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~365
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=770d24a2916696dca7e12e680e458010e184ab8a;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 56cddb49f..4d2581b43 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -52,3 +52,22 @@ People coordinating different tasks. This doesn't mean exclusive work on these a
 * Tobias:
 * Alexandre: binutils-svp64-assembler
 
+# Adding SV
+
+order: listed in [[sv/overview]]
+
+## sv.setvl
+
+a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.
+
+* ISACaller: TODO
+* power-gem5: TODO
+* TestIssuer: TODO
+
+## VL for-loop
+
+main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1
+
+* ISACaller: TODO
+* power-gem5: TODO
+* TestIssuer: TODO