From: Anthony Green <green@redhat.com>
Date: Sun, 10 May 2009 13:25:57 +0000 (+0000)
Subject: Add missing break statemenets.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77176dfc67dc5b8d8984af31ae195b95bac8f8e5;p=binutils-gdb.git

Add missing break statemenets.
---

diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index fdad6c5b223..c528de31846 100644
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,7 @@
+2009-05-09  Anthony Green  <green@moxielogic.com>
+
+	* interp.c (sim_resume): Add missing breaks in switch.
+
 2008-10-03  Anthony Green  <green@moxielogic.com>
 
 	* interp.c (sim_resume): Add support for ldo.b, sto.b, ldo.s, sto.s.
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 2be561ce33c..dd87648b5ff 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -460,6 +460,7 @@ sim_resume (sd, step, siggnal)
 		    TRACE("gsr");
 		    cpu.asregs.regs[a] = cpu.asregs.sregs[v];
 		  }
+		  break;
 		case 0x03: /* ssr */
 		  {
 		    int a = (inst >> 8) & 0xf;
@@ -467,6 +468,7 @@ sim_resume (sd, step, siggnal)
 		    TRACE("ssr");
 		    cpu.asregs.sregs[v] = cpu.asregs.regs[a];
 		  }
+		  break;
 		default:
 		  TRACE("SIGILL2");
 		  cpu.asregs.exception = SIGILL;