From: Megan Wachs <megan@sifive.com>
Date: Tue, 14 Mar 2017 21:52:39 +0000 (-0700)
Subject: Adjust JTAG for rocket-chip changes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77246eaada9532ff5f7dad1d4e293ac8b054236a;p=sifive-blocks.git

Adjust JTAG for rocket-chip changes
---

diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala
index d16cf32..947955f 100644
--- a/src/main/scala/devices/gpio/JTAG.scala
+++ b/src/main/scala/devices/gpio/JTAG.scala
@@ -19,21 +19,22 @@ class JTAGPinsIO extends Bundle {
   val TMS    = new GPIOPin()
   val TDI    = new GPIOPin()
   val TDO    = new GPIOPin()
-  val TRSTn = new GPIOPin()
+  val TRSTn  = new GPIOPin()
 
 }
 
 class JTAGGPIOPort()(implicit p: Parameters) extends Module {
 
   val io = new Bundle {
-    val jtag = new JTAGIO()
+    // TODO: make this not hard-coded true.
+    val jtag = new JTAGIO(hasTRSTn = true)
     val pins = new JTAGPinsIO()
   }
 
   io.jtag.TCK  := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
   io.jtag.TMS  := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
   io.jtag.TDI  := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
-  io.jtag.TRSTn := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
+  io.jtag.TRSTn.get := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
 
   GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
   io.pins.TDO.o.oe := io.jtag.TDO.driven