From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Apr 2019 23:19:19 +0000 (+0100)
Subject: add comment about L1_size being overridden
X-Git-Tag: div_pipeline~2274
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=772b0e49db3f65e219d7889c7e984a99c036f8d1;p=soc.git

add comment about L1_size being overridden
---

diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index 3f1bcb43..0b5e8206 100644
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -27,7 +27,7 @@ class TLB():
         # Internal
         self.state = 0
         # L1 Cache Modules
-        L1_size = 8
+        L1_size = 8 # XXX overridden incoming argument?
         self.cam_L1 = Cam(vma_size, L1_size)
         self.mem_L1 = Memory(asid_size + pte_size, L1_size)