From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 5 Mar 2007 14:55:09 +0000 (+0000)
Subject: Added stub implementations or prototypes for all the functions in this file.
X-Git-Tag: m5_2.0_beta3~154
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7730af9503f1487ff2989f8a5f7708166f7b64f7;p=gem5.git

Added stub implementations or prototypes for all the functions in this file.

--HG--
extra : convert_revision : c0170eae8aeae130f81618ae49a60f879c2b523f
---

diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index e898312ba..b110a1072 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -58,10 +58,73 @@
 #ifndef __ARCH_X86_UTILITY_HH__
 #define __ARCH_X86_UTILITY_HH__
 
-#error X86 is not yet supported!
+#include "arch/x86/types.hh"
+#include "base/misc.hh"
+
+class ThreadContext;
 
 namespace X86ISA
 {
+    static inline bool
+    inUserMode(ThreadContext *tc)
+    {
+        return false;
+    }
+
+    inline ExtMachInst
+    makeExtMI(MachInst inst, ThreadContext * xc) {
+        return inst;
+    }
+
+    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return false;
+    }
+
+    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return false;
+    }
+
+    inline bool isCallerSaveFloatRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return false;
+    }
+
+    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return false;
+    }
+
+    // Instruction address compression hooks
+    inline Addr realPCToFetchPC(const Addr &addr)
+    {
+        return addr;
+    }
+
+    inline Addr fetchPCToRealPC(const Addr &addr)
+    {
+        return addr;
+    }
+
+    // the size of "fetched" instructions (not necessarily the size
+    // of real instructions for PISA)
+    inline size_t fetchInstSize()
+    {
+        return sizeof(MachInst);
+    }
+
+    /**
+     * Function to insure ISA semantics about 0 registers.
+     * @param tc The thread context.
+     */
+    template <class TC>
+    void zeroRegisters(TC *tc);
+
+    inline void initCPU(ThreadContext *tc, int cpuId)
+    {
+        panic("initCPU not implemented!\n");
+    }
 };
 
 #endif // __ARCH_X86_UTILITY_HH__