From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat, 12 Mar 2011 21:57:17 +0000 (+0100)
Subject: i915g: fix transfer coherency
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7735f8c6e525da0ea830f5a54a329abe2d6a1006;p=mesa.git

i915g: fix transfer coherency

The kernel drm takes care of all coherency as long as we don't forget
to submit all outstanding commands in the batchbuffer ...

Also move batchbuffer initialization up because otherwise transfers
for some helper textures fail with a segmentation fault.

And kill the dead code, flushes should now be correct everywhere.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/src/gallium/drivers/i915/i915_context.c b/src/gallium/drivers/i915/i915_context.c
index 5dbf0cfcbf1..cb3de82a104 100644
--- a/src/gallium/drivers/i915/i915_context.c
+++ b/src/gallium/drivers/i915/i915_context.c
@@ -151,6 +151,10 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    util_slab_create(&i915->transfer_pool, sizeof(struct pipe_transfer),
                     16, UTIL_SLAB_SINGLETHREADED);
 
+   /* Batch stream debugging is a bit hacked up at the moment:
+    */
+   i915->batch = i915->iws->batchbuffer_create(i915->iws);
+
    /*
     * Create drawing context and plug our rendering stage into it.
     */
@@ -183,9 +187,5 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    i915->dynamic_dirty = ~0;
    i915->flush_dirty = 0;
 
-   /* Batch stream debugging is a bit hacked up at the moment:
-    */
-   i915->batch = i915->iws->batchbuffer_create(i915->iws);
-
    return &i915->base;
 }
diff --git a/src/gallium/drivers/i915/i915_flush.c b/src/gallium/drivers/i915/i915_flush.c
index 87966d98079..a5407cfd184 100644
--- a/src/gallium/drivers/i915/i915_flush.c
+++ b/src/gallium/drivers/i915/i915_flush.c
@@ -45,28 +45,6 @@ static void i915_flush_pipe( struct pipe_context *pipe,
 
    draw_flush(i915->draw);
 
-#if 0
-   /* Do we need to emit an MI_FLUSH command to flush the hardware
-    * caches?
-    */
-   /* XXX These flags are now implicit. All of them. */
-   if (flags & (PIPE_FLUSH_RENDER_CACHE | PIPE_FLUSH_TEXTURE_CACHE)) {
-      unsigned flush = MI_FLUSH;
-      
-      if (!(flags & PIPE_FLUSH_RENDER_CACHE))
-	 flush |= INHIBIT_FLUSH_RENDER_CACHE;
-
-      if (flags & PIPE_FLUSH_TEXTURE_CACHE)
-	 flush |= FLUSH_MAP_CACHE;
-
-      if (!BEGIN_BATCH(1)) {
-	 FLUSH_BATCH(NULL);
-	 assert(BEGIN_BATCH(1));
-      }
-      OUT_BATCH( flush );
-   }
-#endif
-
    if (i915->batch->map == i915->batch->ptr) {
       return;
    }
diff --git a/src/gallium/drivers/i915/i915_resource_texture.c b/src/gallium/drivers/i915/i915_resource_texture.c
index cfb72e9dcac..7816925d230 100644
--- a/src/gallium/drivers/i915/i915_resource_texture.c
+++ b/src/gallium/drivers/i915/i915_resource_texture.c
@@ -759,6 +759,9 @@ i915_texture_transfer_map(struct pipe_context *pipe,
       assert(box->z == 0);
    offset = i915_texture_offset(tex, transfer->level, box->z);
 
+   /* TODO this is a sledgehammer */
+   pipe->flush(pipe, NULL);
+
    map = iws->buffer_map(iws, tex->buffer,
                          (transfer->usage & PIPE_TRANSFER_WRITE) ? TRUE : FALSE);
    if (map == NULL)