From: lkcl <lkcl@web>
Date: Mon, 26 Oct 2020 09:46:07 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1956
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7739c897d25f80f7bbdbb15a077770a315ab6c3a;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index a78195a29..140867672 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -5,6 +5,7 @@ Fundamental design principles:
 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
+* Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
 
 Advantages of these design principles: