From: Gabe Black Date: Sat, 13 Oct 2018 08:25:30 +0000 (-0700) Subject: arm: Get rid of some register type definitions. X-Git-Tag: v19.0.0.0~1238 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=774770a6410abb129e2a19de1ca50d7c0c311fef;p=gem5.git arm: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 3d98aeacf..ba7c09509 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -391,7 +391,7 @@ ISA::startup(ThreadContext *tc) } -MiscReg +RegVal ISA::readMiscRegNoEffect(int misc_reg) const { assert(misc_reg < NumMiscRegs); @@ -415,7 +415,7 @@ ISA::readMiscRegNoEffect(int misc_reg) const } -MiscReg +RegVal ISA::readMiscReg(int misc_reg, ThreadContext *tc) { CPSR cpsr = 0; @@ -470,7 +470,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) if (!nsacr.cp11) cpacrMask.cp11 = 0; } } - MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); + RegVal val = readMiscRegNoEffect(MISCREG_CPACR); val &= cpacrMask; DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", miscRegName[misc_reg], val); @@ -647,7 +647,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) return 0x04; // DC ZVA clear 64-byte chunks case MISCREG_HCPTR: { - MiscReg val = readMiscRegNoEffect(misc_reg); + RegVal val = readMiscRegNoEffect(misc_reg); // The trap bit associated with CP14 is defined as RAZ val &= ~(1 << 14); // If a CP bit in NSACR is 0 then the corresponding bit in @@ -656,7 +656,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) inSecureState(readMiscRegNoEffect(MISCREG_SCR), readMiscRegNoEffect(MISCREG_CPSR)); if (!secure_lookup) { - MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); + RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); val |= (mask ^ 0x7FFF) & 0xBFFF; } // Set the bits for unimplemented coprocessors to RAO/WI @@ -710,7 +710,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) } void -ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) +ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val) { assert(misc_reg < NumMiscRegs); @@ -732,10 +732,10 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) } void -ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) +ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc) { - MiscReg newVal = val; + RegVal newVal = val; bool secure_lookup; SCR scr; @@ -801,7 +801,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } } - MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); + RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); newVal &= cpacrMask; newVal |= old_val & ~cpacrMask; DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", @@ -994,7 +994,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) SCTLR sctlr = miscRegs[sctlr_idx]; SCTLR new_sctlr = newVal; new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; - miscRegs[sctlr_idx] = (MiscReg)new_sctlr; + miscRegs[sctlr_idx] = (RegVal)new_sctlr; getITBPtr(tc)->invalidateMiscReg(); getDTBPtr(tc)->invalidateMiscReg(); } @@ -1563,8 +1563,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) inSecureState(readMiscRegNoEffect(MISCREG_SCR), readMiscRegNoEffect(MISCREG_CPSR)); if (!secure_lookup) { - MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); - MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; + RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); + RegVal mask = + (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; newVal = (newVal & ~mask) | (oldValue & mask); } break; @@ -1669,7 +1670,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); HCR hcr = readMiscRegNoEffect(MISCREG_HCR); - MiscReg newVal; + RegVal newVal; if (fault == NoFault) { Addr paddr = req->getPaddr(); if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || @@ -1923,7 +1924,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, tranType); - MiscReg newVal; + RegVal newVal; if (fault == NoFault) { Addr paddr = req->getPaddr(); uint64_t attr = getDTBPtr(tc)->getAttr(); diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 2b1bdcb4a..c365a1bd0 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -362,7 +362,7 @@ namespace ArmISA void initializeMiscRegMetadata(); - MiscReg miscRegs[NumMiscRegs]; + RegVal miscRegs[NumMiscRegs]; const IntRegIndex *intRegMap; void @@ -428,10 +428,10 @@ namespace ArmISA void initID64(const ArmISAParams *p); public: - MiscReg readMiscRegNoEffect(int misc_reg) const; - MiscReg readMiscReg(int misc_reg, ThreadContext *tc); - void setMiscRegNoEffect(int misc_reg, const MiscReg &val); - void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc); + RegVal readMiscRegNoEffect(int misc_reg) const; + RegVal readMiscReg(int misc_reg, ThreadContext *tc); + void setMiscRegNoEffect(int misc_reg, const RegVal &val); + void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc); RegId flattenRegId(const RegId& regId) const diff --git a/src/arch/arm/isa_device.cc b/src/arch/arm/isa_device.cc index 110104fe4..60c0d21e7 100644 --- a/src/arch/arm/isa_device.cc +++ b/src/arch/arm/isa_device.cc @@ -58,14 +58,14 @@ BaseISADevice::setISA(ISA *_isa) } void -DummyISADevice::setMiscReg(int misc_reg, MiscReg val) +DummyISADevice::setMiscReg(int misc_reg, RegVal val) { warn("Ignoring write of 0x%lx to miscreg %s\n", val, miscRegName[misc_reg]); } -MiscReg +RegVal DummyISADevice::readMiscReg(int misc_reg) { warn("Returning zero for read from miscreg %s\n", miscRegName[misc_reg]); diff --git a/src/arch/arm/isa_device.hh b/src/arch/arm/isa_device.hh index 374f105c1..60372de02 100644 --- a/src/arch/arm/isa_device.hh +++ b/src/arch/arm/isa_device.hh @@ -72,7 +72,7 @@ class BaseISADevice * @param misc_reg Register number (see miscregs.hh) * @param val Value to store */ - virtual void setMiscReg(int misc_reg, MiscReg val) = 0; + virtual void setMiscReg(int misc_reg, RegVal val) = 0; /** * Read a system register belonging to this device. @@ -80,7 +80,7 @@ class BaseISADevice * @param misc_reg Register number (see miscregs.hh) * @return Register value. */ - virtual MiscReg readMiscReg(int misc_reg) = 0; + virtual RegVal readMiscReg(int misc_reg) = 0; protected: ISA *isa; @@ -100,8 +100,8 @@ class DummyISADevice : public BaseISADevice : BaseISADevice() {} ~DummyISADevice() {} - void setMiscReg(int misc_reg, MiscReg val) override; - MiscReg readMiscReg(int misc_reg) override; + void setMiscReg(int misc_reg, RegVal val) override; + RegVal readMiscReg(int misc_reg) override; }; } diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc index 90d9f1a08..f6cf87294 100644 --- a/src/arch/arm/pmu.cc +++ b/src/arch/arm/pmu.cc @@ -54,7 +54,7 @@ namespace ArmISA { -const MiscReg PMU::reg_pmcr_wr_mask = 0x39; +const RegVal PMU::reg_pmcr_wr_mask = 0x39; PMU::PMU(const ArmPMUParams *p) : SimObject(p), BaseISADevice(), @@ -189,7 +189,7 @@ PMU::regProbeListeners() } void -PMU::setMiscReg(int misc_reg, MiscReg val) +PMU::setMiscReg(int misc_reg, RegVal val) { DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n", miscRegName[unflattenMiscReg(misc_reg)], val); @@ -297,16 +297,16 @@ PMU::setMiscReg(int misc_reg, MiscReg val) miscRegName[misc_reg]); } -MiscReg +RegVal PMU::readMiscReg(int misc_reg) { - MiscReg val(readMiscRegInt(misc_reg)); + RegVal val(readMiscRegInt(misc_reg)); DPRINTF(PMUVerbose, "readMiscReg(%s): 0x%x\n", miscRegName[unflattenMiscReg(misc_reg)], val); return val; } -MiscReg +RegVal PMU::readMiscRegInt(int misc_reg) { misc_reg = unflattenMiscReg(misc_reg); @@ -645,7 +645,7 @@ PMU::setCounterTypeRegister(CounterId id, PMEVTYPER_t val) } void -PMU::setOverflowStatus(MiscReg new_val) +PMU::setOverflowStatus(RegVal new_val) { const bool int_old = reg_pmovsr != 0; const bool int_new = new_val != 0; diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh index ee68272e7..de931eeb2 100644 --- a/src/arch/arm/pmu.hh +++ b/src/arch/arm/pmu.hh @@ -121,14 +121,14 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { * @param misc_reg Register number (see miscregs.hh) * @param val Value to store */ - void setMiscReg(int misc_reg, MiscReg val) override; + void setMiscReg(int misc_reg, RegVal val) override; /** * Read a register within the PMU. * * @param misc_reg Register number (see miscregs.hh) * @return Register value. */ - MiscReg readMiscReg(int misc_reg) override; + RegVal readMiscReg(int misc_reg) override; protected: // PMU register types and constants BitUnion32(PMCR_t) @@ -196,7 +196,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { typedef unsigned int EventTypeId; protected: /* High-level register and interrupt handling */ - MiscReg readMiscRegInt(int misc_reg); + RegVal readMiscRegInt(int misc_reg); /** * PMCR write handling @@ -284,7 +284,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { * * @param new_val New value of the Overflow Status Register */ - void setOverflowStatus(MiscReg new_val); + void setOverflowStatus(RegVal new_val); protected: /* Probe handling and counter state */ struct CounterState; @@ -570,7 +570,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { protected: /* State that needs to be serialized */ /** Performance Monitor Count Enable Register */ - MiscReg reg_pmcnten; + RegVal reg_pmcnten; /** Performance Monitor Control Register */ PMCR_t reg_pmcr; @@ -579,10 +579,10 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { PMSELR_t reg_pmselr; /** Performance Monitor Interrupt Enable Register */ - MiscReg reg_pminten; + RegVal reg_pminten; /** Performance Monitor Overflow Status Register */ - MiscReg reg_pmovsr; + RegVal reg_pmovsr; /** * Performance counter ID register @@ -616,7 +616,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { PMCR_t reg_pmcr_conf; /** PMCR write mask when accessed from the guest */ - static const MiscReg reg_pmcr_wr_mask; + static const RegVal reg_pmcr_wr_mask; /** Performance monitor interrupt number */ ArmInterruptPin *const interrupt; diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 095bd3e53..553bac521 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -482,21 +482,21 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); } -ArmISA::IntReg +RegVal ArmProcess32::getSyscallArg(ThreadContext *tc, int &i) { assert(i < 6); return tc->readIntReg(ArgumentReg0 + i++); } -ArmISA::IntReg +RegVal ArmProcess64::getSyscallArg(ThreadContext *tc, int &i) { assert(i < 8); return tc->readIntReg(ArgumentReg0 + i++); } -ArmISA::IntReg +RegVal ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) { assert(width == 32 || width == 64); @@ -515,7 +515,7 @@ ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) return val; } -ArmISA::IntReg +RegVal ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) { return getSyscallArg(tc, i); @@ -523,14 +523,14 @@ ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) void -ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) +ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val) { assert(i < 6); tc->setIntReg(ArgumentReg0 + i, val); } void -ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) +ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val) { assert(i < 8); tc->setIntReg(ArgumentReg0 + i, val); diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh index 2b4786cce..bdd82f847 100644 --- a/src/arch/arm/process.hh +++ b/src/arch/arm/process.hh @@ -87,10 +87,11 @@ class ArmProcess32 : public ArmProcess public: - ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width) override; - ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; - void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) override; - void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value) override; + RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; + RegVal getSyscallArg(ThreadContext *tc, int &i) override; + void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; + void setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) override; }; class ArmProcess64 : public ArmProcess @@ -106,10 +107,11 @@ class ArmProcess64 : public ArmProcess public: - ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width) override; - ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; - void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) override; - void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value) override; + RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; + RegVal getSyscallArg(ThreadContext *tc, int &i) override; + void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; + void setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) override; }; #endif // __ARM_PROCESS_HH__ diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 3e0a74e69..8346f454b 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -59,12 +59,6 @@ const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + using ArmISAInst::MaxInstDestRegs; using ArmISAInst::MaxMiscDestRegs; -typedef RegVal IntReg; - -// floating point register file entry type -typedef RegVal FloatRegBits; -typedef FloatRegVal FloatReg; - // Number of VecElem per Vector Register, computed based on the vector length constexpr unsigned NumVecElemPerVecReg = 4; using VecElem = uint32_t; @@ -72,9 +66,6 @@ using VecReg = ::VecRegT; using ConstVecReg = ::VecRegT; using VecRegContainer = VecReg::Container; -// cop-0/cop-1 system control register -typedef RegVal MiscReg; - // condition code register; must be at least 32 bits for FpCondCodes typedef uint64_t CCReg;