From: Jonathan Marek Date: Tue, 7 Jul 2020 04:08:33 +0000 (-0400) Subject: freedreno/regs: update primitive output related registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7748afbb1ed778b4242433843557c37de7a81c8c;p=mesa.git freedreno/regs: update primitive output related registers Signed-off-by: Jonathan Marek Part-of: --- diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml index 84c939edac4..6c74e19352a 100644 --- a/src/freedreno/registers/a6xx.xml +++ b/src/freedreno/registers/a6xx.xml @@ -1914,9 +1914,13 @@ to upconvert to 32b float internally? - - - + + + + + + + @@ -1988,14 +1992,12 @@ to upconvert to 32b float internally? - - - - - - - - + + + + + + @@ -2551,18 +2553,28 @@ to upconvert to 32b float internally? - - - - - - + + + + + + + + + - + - + + + + + + - @@ -2620,7 +2632,7 @@ to upconvert to 32b float internally? - + num of varyings plus four for gl_Position (plus one if gl_PointSize) plus # of transform-feedback (streamout) varyings if using the @@ -2628,43 +2640,11 @@ to upconvert to 32b float internally? - - - - - - num of varyings plus four for gl_Position (plus one if gl_PointSize) - plus # of transform-feedback (streamout) varyings if using the - hw streamout (rather than stg instructions in shader) - - - - - - - - - - domain shader version of VPC_PACK - - - - - - + + + + @@ -2753,49 +2733,25 @@ to upconvert to 32b float internally? - - - vertex shader + + num of varyings plus four for gl_Position (plus one if gl_PointSize) plus # of transform-feedback (streamout) varyings if using the hw streamout (rather than stg instructions in shader) - - - - - geometry shader - - - + - - - - - hull shader? + + - num of varyings plus four for gl_Position (plus one if gl_PointSize) - plus # of transform-feedback (streamout) varyings if using the - hw streamout (rather than stg instructions in shader) - - - - - - - domain shader - num of varyings plus four for gl_Position (plus one if gl_PointSize) - plus # of transform-feedback (streamout) varyings if using the - hw streamout (rather than stg instructions in shader) - - - - + + + + @@ -2967,9 +2923,9 @@ to upconvert to 32b float internally? bit N corresponds to brac.N --> - + - + @@ -3014,7 +2970,7 @@ to upconvert to 32b float internally? - + @@ -3051,9 +3007,9 @@ to upconvert to 32b float internally? --> - + - + diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index 9424704a9d2..4c18a66cc8a 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -525,7 +525,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t num_ .vp_xform_disable = 1, .vp_clip_code_ignore = 1, .clip_disable = 1), - A6XX_GRAS_UNKNOWN_8001(0)); + A6XX_GRAS_VS_CL_CNTL(0)); tu_cs_emit_regs(cs, A6XX_GRAS_SU_CNTL()); // XXX msaa enable? tu_cs_emit_regs(cs, diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index cb207f0b059..de1a672b094 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -746,7 +746,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5); - tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff); + tu_cs_emit_write_reg(cs, REG_A6XX_VPC_VS_LAYER_CNTL, 0x0000ffff); /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */ tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX); @@ -769,7 +769,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0); tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0); - tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00); + tu_cs_emit_write_reg(cs, REG_A6XX_VPC_VS_CLIP_CNTL, 0xffff00); tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0); tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, @@ -791,7 +791,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0); tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0); - tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0); + tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_VS_LAYER_CNTL, 0); tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2); tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0); tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0); diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index c22cadb6ffa..74ab7872e9d 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -822,10 +822,10 @@ tu6_emit_vpc(struct tu_cs *cs, A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) | A6XX_VPC_CNTL_0_UNKLOC(0xff)); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1); - tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) | - A6XX_VPC_PACK_PSIZELOC(pointsize_loc) | - A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc)); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VS_PACK, 1); + tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) | + A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) | + A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc)); if (hs) { shader_info *hs_info = &hs->shader->nir->info; @@ -875,33 +875,33 @@ tu6_emit_vpc(struct tu_cs *cs, A6XX_PC_TESS_CNTL_OUTPUT(output)); /* xxx: Misc tess unknowns: */ - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9103, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_DS_CLIP_CNTL, 1); tu_cs_emit(cs, 0x00ffff00); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9106, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_DS_LAYER_CNTL, 1); tu_cs_emit(cs, 0x0000ffff); - tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809D, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DS_LAYER_CNTL, 1); tu_cs_emit(cs, 0x0); - tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8002, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DS_CL_CNTL, 1); tu_cs_emit(cs, 0x0); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1); - tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) | - A6XX_VPC_PACK_PSIZELOC(255) | - A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc)); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VS_PACK, 1); + tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) | + A6XX_VPC_VS_PACK_PSIZELOC(255) | + A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc)); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_3, 1); - tu_cs_emit(cs, A6XX_VPC_PACK_3_POSITIONLOC(position_loc) | - A6XX_VPC_PACK_3_PSIZELOC(pointsize_loc) | - A6XX_VPC_PACK_3_STRIDE_IN_VPC(linkage.max_loc)); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_DS_PACK, 1); + tu_cs_emit(cs, A6XX_VPC_DS_PACK_POSITIONLOC(position_loc) | + A6XX_VPC_DS_PACK_PSIZELOC(pointsize_loc) | + A6XX_VPC_DS_PACK_STRIDE_IN_VPC(linkage.max_loc)); tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1); - tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(linkage.cnt)); + tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(linkage.cnt)); - tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1); - tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(linkage.max_loc) | + tu_cs_emit_pkt4(cs, REG_A6XX_PC_DS_OUT_CNTL, 1); + tu_cs_emit(cs, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) | CONDREG(pointsize_regid, 0x100)); tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER); @@ -933,30 +933,30 @@ tu6_emit_vpc(struct tu_cs *cs, uint32_t primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1); - tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) | - A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) | - A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc)); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_PACK, 1); + tu_cs_emit(cs, A6XX_VPC_GS_PACK_POSITIONLOC(position_loc) | + A6XX_VPC_GS_PACK_PSIZELOC(pointsize_loc) | + A6XX_VPC_GS_PACK_STRIDE_IN_VPC(linkage.max_loc)); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1); - tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_LAYER_CNTL, 1); + tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00); - tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_GS_LAYER_CNTL, 1); tu_cs_emit(cs, CONDREG(layer_regid, - A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER)); + A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER)); uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3); - tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1); - tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) | - A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid)); + tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1); + tu_cs_emit(cs, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(linkage.cnt) | + A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid)); - tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1); - tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) | - CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) | - CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) | - CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID)); + tu_cs_emit_pkt4(cs, REG_A6XX_PC_GS_OUT_CNTL, 1); + tu_cs_emit(cs, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) | + CONDREG(pointsize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) | + CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) | + CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID)); tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1); tu_cs_emit(cs, @@ -967,13 +967,13 @@ tu6_emit_vpc(struct tu_cs *cs, tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1); tu_cs_emit(cs, 0); - tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_GS_CL_CNTL, 1); tu_cs_emit(cs, 0); tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1); tu_cs_emit(cs, 0xff); - tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_CLIP_CNTL, 1); tu_cs_emit(cs, 0xffff00); tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1); @@ -986,12 +986,12 @@ tu6_emit_vpc(struct tu_cs *cs, tu_cs_emit(cs, vs->output_size); } - tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1); - tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt)); + tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1); + tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt)); - tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1); - tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) | - (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0)); + tu_cs_emit_pkt4(cs, REG_A6XX_PC_VS_OUT_CNTL, 1); + tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) | + (last_shader->writes_psize ? A6XX_PC_VS_OUT_CNTL_PSIZE : 0)); } static int @@ -2239,7 +2239,7 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder, A6XX_PC_POLYGON_MODE(.mode = mode)); /* move to hw ctx init? */ - tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001()); + tu_cs_emit_regs(&cs, A6XX_GRAS_VS_CL_CNTL()); tu_cs_emit_regs(&cs, A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f), A6XX_GRAS_SU_POINT_SIZE(1.0f)); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index 19f95e85d07..f20666c145b 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -1188,7 +1188,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) WRITE(REG_A6XX_SP_UNKNOWN_B183, 0); WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0); - WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0); + WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0); WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2); WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0); WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 2e61ece1d21..72a47c1f571 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -577,34 +577,33 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) | A6XX_PC_TESS_CNTL_OUTPUT(output)); - /* xxx: Misc tess unknowns: */ - OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1); + OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1); OUT_RING(ring, 0x00ffff00); - OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1); + OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1); OUT_RING(ring, 0x0000ffff); - OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1); + OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1); OUT_RING(ring, 0x0); - OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1); + OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1); OUT_RING(ring, 0x0); - OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1); - OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) | - A6XX_VPC_PACK_PSIZELOC(255) | - A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc)); + OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1); + OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) | + A6XX_VPC_VS_PACK_PSIZELOC(255) | + A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc)); - OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1); - OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) | - A6XX_VPC_PACK_3_PSIZELOC(psize_loc) | - A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc)); + OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1); + OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) | + A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) | + A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc)); OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1); - OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt)); + OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt)); - OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1); - OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) | + OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1); + OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) | CONDREG(psize_regid, 0x100)); } else { @@ -612,8 +611,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, OUT_RING(ring, 0); } - OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1); - OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt)); + OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1); + OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt)); bool enable_varyings = fs->total_in > 0; @@ -623,9 +622,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) | A6XX_VPC_CNTL_0_UNKLOC(0xff)); - OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1); - OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) | - CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE)); + OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1); + OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) | + CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE)); OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1); OUT_RING(ring, 0); @@ -663,7 +662,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1); OUT_RING(ring, 0); /* XXX */ - OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1); + OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1); OUT_RING(ring, 0x0000ffff); /* XXX */ bool need_size = fs->frag_face || fs->fragcoord_compmask != 0; @@ -720,10 +719,10 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION)); } - OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1); - OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) | - A6XX_VPC_PACK_PSIZELOC(psize_loc) | - A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc)); + OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1); + OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) | + A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) | + A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc)); if (gs) { OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1); @@ -741,28 +740,28 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, else fd6_emit_link_map(screen, vs, gs, ring); - OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1); - OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) | - A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) | - A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc)); + OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1); + OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) | + A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) | + A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc)); - OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1); - OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00); + OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1); + OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00); - OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1); - OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER)); + OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1); + OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER)); uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3); - OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1); - OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) | - A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid)); + OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1); + OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) | + A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid)); - OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1); - OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) | - CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) | - CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) | - CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID)); + OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1); + OUT_RING(ring, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) | + CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) | + CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) | + CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID)); uint32_t output; switch (gs->shader->nir->info.gs.output_primitive) { @@ -784,13 +783,13 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) | A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1)); - OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1); + OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1); OUT_RING(ring, 0); OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1); OUT_RING(ring, 0xff); - OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1); + OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1); OUT_RING(ring, 0xffff00); const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs; @@ -814,7 +813,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, OUT_RING(ring, 0); } - OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1); + OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1); OUT_RING(ring, 0xffff00); OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c index 3ff5d83af68..4d9ecf27b85 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c @@ -56,7 +56,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, .vp_clip_code_ignore = 1, .zero_gb_scale_z = cso->clip_halfz ), - A6XX_GRAS_UNKNOWN_8001()); + A6XX_GRAS_VS_CL_CNTL()); OUT_REG(ring, A6XX_GRAS_SU_CNTL(