From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 9 May 2021 14:57:09 +0000 (+0100)
Subject: add ld/st misalignment test case
X-Git-Tag: 0.0.3~67
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=774991a32a404389de594ad1df0bcbc7e2d5aca7;p=openpower-isa.git

add ld/st misalignment test case
---

diff --git a/src/openpower/test/ldst/ldst_exc_cases.py b/src/openpower/test/ldst/ldst_exc_cases.py
new file mode 100644
index 00000000..5cd2086e
--- /dev/null
+++ b/src/openpower/test/ldst/ldst_exc_cases.py
@@ -0,0 +1,19 @@
+from openpower.simulator.program import Program
+from openpower.endian import bigendian
+from openpower.test.common import TestAccumulatorBase
+
+
+class LDSTExceptionTestCase(TestAccumulatorBase):
+
+    def case_1_load_misalign(self):
+        lst = ["ldx 3, 1, 0"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xFFFFFFFFFFFFFFFF # deliberately misaligned
+        initial_regs[2] = 0x0008
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        self.add_case(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+