From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 19 Feb 2020 13:58:55 +0000 (+0100)
Subject: soc_core: fix missing init on main_ram
X-Git-Tag: 24jan2021_ls180~651
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=774a55a2aa7cefe6f617cce38697822508325c27;p=litex.git

soc_core: fix missing init on main_ram
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 7ba7b49e..e3f78e0d 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -168,7 +168,7 @@ class SoCCore(LiteXSoC):
 
         # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
         if integrated_main_ram_size:
-            self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size)
+            self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size, integrated_main_ram_init)
 
         # Add Identifier
         if ident != "":