From: Daniel R. Carvalho Date: Thu, 29 Nov 2018 15:33:24 +0000 (+0100) Subject: mem-cache: Fix recvTimingReq doWritebacks tick X-Git-Tag: v19.0.0.0~1072 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7770e6a972d8dd8742724533fe4c4635d8aabf2c;p=gem5.git mem-cache: Fix recvTimingReq doWritebacks tick Before being sent to the writebuffer, the evicted blocks must be selected for replacement, and therefore the access latency must be applied. The forward latency is then applied on top of that delay. Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14736 Reviewed-by: Jason Lowe-Power Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index d4e93c0ef..204377044 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -355,9 +355,10 @@ BaseCache::recvTimingReq(PacketPtr pkt) // access() will set the lat value. satisfied = access(pkt, blk, lat, writebacks); - // copy writebacks to write buffer here to ensure they logically - // precede anything happening below - doWritebacks(writebacks, forward_time); + // After the evicted blocks are selected, they must be forwarded + // to the write buffer to ensure they logically precede anything + // happening below + doWritebacks(writebacks, clockEdge(lat + forwardLatency)); } // Here we charge the headerDelay that takes into account the latencies