From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 8 Aug 2014 13:41:07 +0000 (+0800)
Subject: sdramphy/gensdrphy: fix rddata_en generation
X-Git-Tag: 24jan2021_ls180~2678
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=777ebb78753e9f8cf0a4fcf50a4af82f56c3b195;p=litex.git

sdramphy/gensdrphy: fix rddata_en generation
---

diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdramphy/gensdrphy.py
index 800dc0d5..b2530fd3 100644
--- a/misoclib/sdramphy/gensdrphy.py
+++ b/misoclib/sdramphy/gensdrphy.py
@@ -72,11 +72,12 @@ class GENSDRPHY(Module):
 		drive_dq = Signal()
 		self.sync += sd_dq_out.eq(self.dfi.p0.wrdata),
 		self.specials += Tristate(pads.dq, sd_dq_out, drive_dq)
-		self.sync += If(self.dfi.p0.wrdata_en,
-			pads.dm.eq(self.dfi.p0.wrdata_mask)
-		).Else(
-			pads.dm.eq(0)
-		)
+		self.sync += \
+			If(self.dfi.p0.wrdata_en,
+				pads.dm.eq(self.dfi.p0.wrdata_mask)
+			).Else(
+				pads.dm.eq(0)
+			)
 		sd_dq_in_ps = Signal(d)
 		self.sync.sys_ps += sd_dq_in_ps.eq(pads.dq)
 		self.sync += self.dfi.p0.rddata.eq(sd_dq_in_ps)
@@ -89,5 +90,5 @@ class GENSDRPHY(Module):
 		self.comb += drive_dq.eq(d_dfi_wrdata_en)
 
 		rddata_sr = Signal(4)
-		self.comb += self.dfi.p0.rddata_valid.eq(rddata_sr[0])
-		self.sync += rddata_sr.eq(Cat(self.dfi.p0.rddata_en, rddata_sr[1:]))
+		self.comb += self.dfi.p0.rddata_valid.eq(rddata_sr[3])
+		self.sync += rddata_sr.eq(Cat(self.dfi.p0.rddata_en, rddata_sr[:3]))