From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 16:20:20 +0000 (+0100)
Subject: halve the test memory size again
X-Git-Tag: div_pipeline~261
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7785ed05f8f353dc439b0ec910cef1000a9d59a2;p=soc.git

halve the test memory size again
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index bd3422f0..4bb6aafd 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -206,7 +206,7 @@ class TestMemoryPortInterface(Elaboratable):
 
     def __init__(self, regwid=64, addrwid=4):
         # hard-code memory addressing width to 6 bits
-        self.mem = TestMemory(regwid, 6, granularity=regwid//8,
+        self.mem = TestMemory(regwid, 5, granularity=regwid//8,
                               init=False)
         self.regwid = regwid
         self.addrwid = addrwid