From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 20:09:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2528
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7797ccb4fc73bc8950232dac596f5d8962ac3188;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 12deeaccf..1a8bdc840 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -68,8 +68,10 @@ may be performed by setting VL=8, and a one-instruction
 SV is primarily designed for use as an efficient hybrid 3D GPU / VPU /
 CPU ISA.
 
-Vectorisation of the VSX Packed SIMD system
-likewise makes no sense whatsoever. SV *replaces* VSX and provides,
+Vectorisation of the VSX Packed SIMD system makes no sense whatsoever,
+the sole exceptions potentially being any operations with 128-bit
+operands.
+SV effectively *replaces* VSX and provides,
 at the very minimum, predication (which VSX was designed without).
 Thus all VSX Major Opcodes - all of them - are "unused" and must raise
 illegal instruction exceptions in SV Prefix Mode.