From: lkcl <lkcl@web>
Date: Thu, 16 Jun 2022 17:36:06 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1751
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7799485e5a26ee07256dfdab6d4ccb13ef68f923;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 7719e5585..dde041da5 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -93,7 +93,8 @@ Given that XYZW Swizzle can select simultaneously between one *and four*
 register operands, a full version of this instruction would
 be an eye-popping 8 64-bit operands: 4-in, 4-out. As part of a Scalar
 ISA this not practical. A compromise is to cut the registers required
-by half.
+by half, placing it on-par with `lq`, `stq` and Indexed
+Load-with-update instructions.
 When part of the Scalar Power ISA (not SVP64 Vectorised)
 mv.swiz and fmv.swiz operate on four 32-bit
 quantities, reducing this instruction to a feasible