From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 22 Apr 2016 16:02:55 +0000 (+0200)
Subject: Added support for "active high" and "active low" latches in BLIF front-end
X-Git-Tag: yosys-0.7~254^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=779e2cc819463fa5bc4ebfee397eb06368eb10b0;p=yosys.git

Added support for "active high" and "active low" latches in BLIF front-end
---

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index a028c4336..a901e55f9 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -244,6 +244,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 					cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
 				else if (!strcmp(edge, "fe"))
 					cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
+				else if (!strcmp(edge, "ah"))
+					cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
+				else if (!strcmp(edge, "al"))
+					cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
 				else {
 			no_latch_clock:
 					cell = module->addCell(NEW_ID, dff_name);