From: Mateusz Holenko <mholenko@antmicro.com>
Date: Tue, 14 Apr 2020 19:43:58 +0000 (+0200)
Subject: soc_core: Fix region type generation
X-Git-Tag: 24jan2021_ls180~458^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77a05b78e81af7fb2ca992ae8b6b5bd550310ec8;p=litex.git

soc_core: Fix region type generation

Include information about being a linker region.
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index b1209a00..3eb0016c 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -244,6 +244,8 @@ class SoCCore(LiteXSoC):
         for region in self.bus.regions.values():
             region.length = region.size
             region.type   = "cached" if region.cached else "io"
+            if region.linker:
+                region.type += "+linker"
         self.csr_regions = self.csr.regions
         for name, value in self.config.items():
             self.add_config(name, value)