From: Glenn Kennard <glenn.kennard@gmail.com>
Date: Tue, 6 Feb 2018 20:24:07 +0000 (+1000)
Subject: r600: clean up initial shader register setup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77b1b337242770f45feea8e1a42c5005590e5358;p=mesa.git

r600: clean up initial shader register setup

This is taken from Glenn Kennards scratch series, but separated
out as a cleanup by me.

Reviewed-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 26f9ddb9401..269d4f0c784 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3344,41 +3344,38 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 	ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
 
 	ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
-	ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
-			ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
-	ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
-	ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
+
+	int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
+			ctx.info.file_max[TGSI_FILE_TEMPORARY];
+	ctx.bc->ar_reg = ++regno;
+	ctx.bc->index_reg[0] = ++regno;
+	ctx.bc->index_reg[1] = ++regno;
 
 	if (ctx.type == PIPE_SHADER_TESS_CTRL) {
-		ctx.tess_input_info = ctx.bc->ar_reg + 3;
-		ctx.tess_output_info = ctx.bc->ar_reg + 4;
-		ctx.temp_reg = ctx.bc->ar_reg + 5;
+		ctx.tess_input_info = ++regno;
+		ctx.tess_output_info = ++regno;
 	} else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
 		ctx.tess_input_info = 0;
-		ctx.tess_output_info = ctx.bc->ar_reg + 3;
-		ctx.temp_reg = ctx.bc->ar_reg + 4;
+		ctx.tess_output_info = ++regno;
 	} else if (ctx.type == PIPE_SHADER_GEOMETRY) {
-		ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
-		ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
-		ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
-		ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
-		ctx.temp_reg = ctx.bc->ar_reg + 7;
+		ctx.gs_export_gpr_tregs[0] = ++regno;
+		ctx.gs_export_gpr_tregs[1] = ++regno;
+		ctx.gs_export_gpr_tregs[2] = ++regno;
+		ctx.gs_export_gpr_tregs[3] = ++regno;
 		if (ctx.shader->gs_tri_strip_adj_fix) {
-			ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
-			ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
-			ctx.temp_reg += 2;
+			ctx.gs_rotated_input[0] = ++regno;
+			ctx.gs_rotated_input[1] = ++regno;
 		} else {
 			ctx.gs_rotated_input[0] = 0;
 			ctx.gs_rotated_input[1] = 1;
 		}
-	} else {
-		ctx.temp_reg = ctx.bc->ar_reg + 3;
 	}
 
 	if (shader->uses_images) {
-		ctx.thread_id_gpr = ctx.temp_reg++;
+		ctx.thread_id_gpr = ++regno;
 		ctx.thread_id_gpr_loaded = false;
 	}
+	ctx.temp_reg = ++regno;
 
 	shader->max_arrays = 0;
 	shader->num_arrays = 0;