From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Sun, 10 Oct 2021 11:07:43 +0000 (+0100)
Subject: fixed code blocks (hopefully)
X-Git-Tag: opf_rfc_ls005_v1~3665
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77c289b2e3614bcce841e127b800fb366ee689ee;p=libreriscv.git

fixed code blocks (hopefully)
---

diff --git a/docs/learning_nmigen.mdwn b/docs/learning_nmigen.mdwn
index 8f21b9b8d..b2f6e1927 100644
--- a/docs/learning_nmigen.mdwn
+++ b/docs/learning_nmigen.mdwn
@@ -22,39 +22,40 @@
 
 1. To the testbench file, add the import statement for the counter module (better get used to separating your sim/stimulus and module classes from the beginning):
 
-    from up_counter import UpCounter
+```from up_counter import UpCounter```
 
 1. Create a file called "conv_to_verilog.py" and copy the code from "Converting a counter" section. Also add the import statement as with the testbench.
 
 1. Generate GTKWave .vcd file by running:
 
-    $python3 tb_up_counter.py
+```$python3 tb_up_counter.py```
 
 1. Launch GTKWave by calling:
 
-    $gtkwave up_counter.vcd
+```$gtkwave up_counter.vcd```
 
 1. Now you should be able to inspect the signals and check counter behaviour (although the test bench also does this).
 
 1. To generate the verilog equivalent, call the file we created earlier. The script will create a up_counter.v verilog file.
 
-    $python3 conv_to_verilog.py
+```$python3 conv_to_verilog.py```
 
 ## Block Digram with Yosys
 
 1. Open yosys in interactive mode and load the generated verilog file. Calling "show" should generate the diagram .dot file (as a temp file "~/.yosys_show.dot") and open it using xdot. *You may need to install xdot separately with apt*. Xdot is **interactive** (you can click on blocks and nodes!).
 
-    $yosys
-    yosys> read_verilog up_counter.v
-    yosys> show
+```$yosys
+yosys> read_verilog up_counter.v
+yosys> show
+```
 
 1. Outside of Yosys, you can run xdot directly:
 
-    $xdot ~/.yosys_show.dot
+```$xdot ~/.yosys_show.dot```
 
 1. If you want to generate a static image, you can use graphviz's "dot" command to generate an image (for example PNG).
 
-    $dot ~/.yosys_show.dot -Tpng -o up_counter.png
+```$dot ~/.yosys_show.dot -Tpng -o up_counter.png```
 
 1. Now you can improve your understanding with the nMigen, verilog, and block diagram views side-by-side!