From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 29 Jul 2014 14:33:56 +0000 (+0200)
Subject: Allow "hierarchy -generate" for $__ cells
X-Git-Tag: yosys-0.4~369
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77e2d39cd079ba98340f55f57e8a6462fb709442;p=yosys.git

Allow "hierarchy -generate" for $__ cells
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index c869ec729..a1361c680 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -41,7 +41,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 	for (auto i2 : i1.second->cells_)
 	{
 		RTLIL::Cell *cell = i2.second;
-		if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0)
+		if (design->has(cell->type))
+			continue;
+		if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__")
 			continue;
 		for (auto &pattern : celltypes)
 			if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE))