From: Luke Kenneth Casson Leighton Date: Fri, 28 Oct 2022 12:13:33 +0000 (+0100) Subject: wording, prepare for adding dsld and dsrd X-Git-Tag: opf_rfc_ls005_v1~37 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77f9269331965847850649e8033e879cec8ca542;p=libreriscv.git wording, prepare for adding dsld and dsrd --- diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index f7e97fd46..e86266505 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -29,10 +29,13 @@ **Summary** +Instructions added + ``` - Instructions added maddedu - Multiply-Add Extended Double Unsigned divmod2du - Divide/Modulo Quad-Double Unsigned + dsld - Double Shift Left Doubleword + dsrd - Double Shift Right Doubleword ``` **Submitter**: Luke Leighton (Libre-SOC) @@ -60,12 +63,12 @@ **Motivation** -Similar to `maddhdu` and `maddld`, but allow for a big-integer rolling -accumulation affect: `RC` effectively becomes a 64-bit carry in chains -of highly-efficient loop-unrolled arbitrary-length big-integer operations. -Similar to `divdeu`, and has similar advantages to `maddedu`, -Modulo result is available with the quotient in a single instruction -allowing highly-efficient arbitrary-length big-integer division. +* Similar to `maddhdu` and `maddld`, but allow for a big-integer rolling + accumulation affect: `RC` effectively becomes a 64-bit carry in chains + of highly-efficient loop-unrolled arbitrary-length big-integer operations. +* Similar to `divdeu`, and has similar advantages to `maddedu`, + Modulo result is available with the quotient in a single instruction + allowing highly-efficient arbitrary-length big-integer division. **Notes and Observations**: @@ -73,12 +76,13 @@ allowing highly-efficient arbitrary-length big-integer division. there is a **pair** of results produced. 2. An overflow variant (XER.OV set) of `divmod2du` would be valuable but VA-Form EXT004 is under severe pressure. -3. Both instructions have been present in Intel x86 for several decades. -4. Neither instruction is present in VSX: these are 128/64 whereas +3. Both `maddhdu` and `divmod2du` instructions have been present in Intel x86 + for several decades. Likewise, variants of `dsld` and `dsrd`. +4. None of these instruction is present in VSX: these are 128/64 whereas VSX is 128/128. 5. `maddedu` and `divmod2du` are full inverses of each other, including - when used for arbitrary-length big-integer arithmetic -6. These are both 3-in 2-out instructions. If Power ISA did not already + when used for arbitrary-length big-integer arithmetic. +6. These are all 3-in 2-out instructions. If Power ISA did not already have LD/ST-with-update instructions and instructions with `RAp` and `RTp` then these instructions would not be proposed.