From: lkcl <lkcl@web>
Date: Sun, 2 Apr 2023 20:11:06 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~172
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78024eec7b76163ca8076580df48e4285b3aa403;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 92521b0ec..df5f3d650 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -115,15 +115,14 @@ with Update instructions either.
 The table for [[sv/svp64]] for `immed(RA)` which is `RM.MODE`
 (bits 19:23 of `RM`) is:
 
-| 0-1 |  2  |  3   4  |  description               |
-| --- | --- |---------|--------------------------- |
-| 00  | 0   |  zz els | simple mode                |
-| 00  | 1   | PI  LF  | post-increment and Fault-First  |
-| 01  | inv | CR-bit  | Rc=1: ffirst CR sel        |
-| 01  | inv | els RC1 |  Rc=0: ffirst z/nonz       |
-| 10  |   N | zz  els |  sat mode: N=0/1 u/s       |
-| 11  | inv | CR-bit  |  Rc=1: pred-result CR sel  |
-| 11  | inv | els RC1 |  Rc=0: pred-result z/nonz  |
+| 0 | 1 |  2  |  3   4  |  description               |
+|---|---| --- |---------|--------------------------- |
+| 0 | 0 | 0   |  zz els | simple mode                |
+| 0 | 0 | 1   | PI  LF  | post-increment and Fault-First  |
+| 1 | 0 |   N | zz  els |  sat mode: N=0/1 u/s       |
+|VLi| 1 | inv | CR-bit  | Rc=1: ffirst CR sel        |
+|VLi| 1 | inv | els RC1 |  Rc=0: ffirst z/nonz       |
+
 
 The `els` bit is only relevant when `RA.isvec` is clear: this indicates
 whether stride is unit or element:
@@ -174,18 +173,16 @@ operation (including a simple mv) in "Splat" mode.*
 The modes for `RA+RB` indexed version are slightly different
 but are the same `RM.MODE` bits (19:23 of `RM`):
 
-| 0-1 |  2  |  3   4  |  description              |
-| --- | --- |---------|-------------------------- |
-| 00  | SEA |  dz  sz | simple mode        |
-| 01  | SEA | dz sz   | Strided (scalar only source)   |
-| 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
-| 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
-| 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
+| 0 | 1 |  2  |  3   4  |  description               |
+|---|---| --- |---------|--------------------------- |
+|els| 0 | SEA |  dz  sz | simple mode        |
+|VLi| 1 | inv | CR-bit  | Rc=1: ffirst CR sel        |
+|VLi| 1 | inv | els RC1 |  Rc=0: ffirst z/nonz       |
 
 Vector Indexed Strided Mode is qualified as follows:
 
 ```
-    if mode = 0b01 and !RA.isvec and !RB.isvec:
+    if els and !RA.isvec and !RB.isvec:
         svctx.ldstmode = elementstride
 ```