From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Feb 2020 16:57:53 +0000 (+0000)
Subject: remove working code, shrink "fail" case
X-Git-Tag: partial-core-ls180-gdsii~215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=780bd0617b4f8356602f6771a2dde245d5661f42;p=soclayout.git

remove working code, shrink "fail" case
---

diff --git a/experiments2/part_sig_add.py b/experiments2/part_sig_add.py
index 284fbf7..ec7bf3b 100644
--- a/experiments2/part_sig_add.py
+++ b/experiments2/part_sig_add.py
@@ -15,14 +15,6 @@ def test():
                                 module.add_output,
                                 module.ls_output,
                                 module.sub_output,
-                                module.eq_output,
-                                module.gt_output,
-                                module.ge_output,
-                                module.ne_output,
-                                module.lt_output,
-                                module.le_output,
-                                module.mux_sel,
-                                module.mux_out,
                                 module.carry_in,
                                 module.add_carry_out,
                                 module.sub_carry_out,
diff --git a/experiments2/test_partsig.py b/experiments2/test_partsig.py
index 093e59b..3c868a4 100644
--- a/experiments2/test_partsig.py
+++ b/experiments2/test_partsig.py
@@ -16,19 +16,9 @@ class TestAddMod2(Elaboratable):
         self.partpoints = partpoints
         self.a = PartitionedSignal(partpoints, width)
         self.b = PartitionedSignal(partpoints, width)
-        self.bsig = Signal(width)
         self.add_output = Signal(width)
         self.ls_output = Signal(width) # left shift
-        self.ls_scal_output = Signal(width) # left shift
         self.sub_output = Signal(width)
-        self.eq_output = Signal(len(partpoints)+1)
-        self.gt_output = Signal(len(partpoints)+1)
-        self.ge_output = Signal(len(partpoints)+1)
-        self.ne_output = Signal(len(partpoints)+1)
-        self.lt_output = Signal(len(partpoints)+1)
-        self.le_output = Signal(len(partpoints)+1)
-        self.mux_sel = Signal(len(partpoints)+1)
-        self.mux_out = Signal(width)
         self.carry_in = Signal(len(partpoints)+1)
         self.add_carry_out = Signal(len(partpoints)+1)
         self.sub_carry_out = Signal(len(partpoints)+1)
@@ -40,13 +30,6 @@ class TestAddMod2(Elaboratable):
         sync = m.d.sync
         self.a.set_module(m)
         self.b.set_module(m)
-        # compares
-        sync += self.lt_output.eq(self.a < self.b)
-        sync += self.ne_output.eq(self.a != self.b)
-        sync += self.le_output.eq(self.a <= self.b)
-        sync += self.gt_output.eq(self.a > self.b)
-        sync += self.eq_output.eq(self.a == self.b)
-        sync += self.ge_output.eq(self.a >= self.b)
         # add
         add_out, add_carry = self.a.add_op(self.a, self.b,
                                            self.carry_in)
@@ -62,10 +45,6 @@ class TestAddMod2(Elaboratable):
         # left shift
         sync += self.ls_output.eq(self.a << self.b)
         ppts = self.partpoints
-        sync += self.mux_out.eq(PMux(m, ppts, self.mux_sel, self.a, self.b))
-        # scalar left shift
-        comb += self.bsig.eq(self.b.sig)
-        sync += self.ls_scal_output.eq(self.a << self.bsig)
 
         return m