From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 17:21:08 +0000 (-0700)
Subject: kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
X-Git-Tag: working-ls180~549^2~34
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7812a2959b9b23b44e8144f9edb139f282d623e1;p=yosys.git

kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
---

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index fb4e0930d..36908868c 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -128,11 +128,9 @@ struct TimingInfo
 				int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
 				int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
 				int max = std::max(rise_max,fall_max);
-				if (max < 0)
-					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-				if (max <= 0) {
-					log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-					continue;
+				if (max < 0) {
+					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
+					max = 0;
 				}
 				for (const auto &d : dst) {
 					auto &v = t.arrival[NameBit(d)];
@@ -152,11 +150,9 @@ struct TimingInfo
 					if (!c.wire->port_input)
 						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
 				int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
-				if (max < 0)
-					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-				if (max <= 0) {
-					log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-					continue;
+				if (max < 0) {
+					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
+					max = 0;
 				}
 				for (const auto &s : src) {
 					auto &v = t.required[NameBit(s)];