From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 14:42:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2539
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7824c04000ce227a5f97d30004a5b2dd23bc014a;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 9ec5bed07..2871bd9bc 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -970,7 +970,12 @@ What, then, of `sv.madded`? If the destination is hard-coded to
 RT and RT+1 the instruction is not useful when Vectorised because
 the output will be overwritten on the next element.  To solve this
 is easy: define the destination registers as RT and RT+MAXVL
-respectively.
+respectively.  This makes it easy for compilers to statically allocate
+registers even when VL changes dynamically.
+
+Bear in mind that both RT and RT+MAXVL are starting points for Vectors,
+and bear in mind that element-width overrides still have to be taken
+into consideration, 
 
 
 * [[isa/svfixedarith]]