From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Oct 2018 03:51:42 +0000 (+0100)
Subject: add 3 registers to sv c.lwsp
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78293796a49a31e79e5abef33c9e140c60d10d89;p=riscv-tests.git

add 3 registers to sv c.lwsp
---

diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S
index db3c94f..d643594 100644
--- a/isa/rv64uc/sv_c_lwsp.S
+++ b/isa/rv64uc/sv_c_lwsp.S
@@ -19,11 +19,12 @@ RVTEST_CODE_BEGIN
 
         li          a2, 0 
         li          a3, 0 
+        li          a4, 0 
 
-        SET_SV_MVL(2)
+        SET_SV_MVL(3)
         SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
                       SV_REG_CSR(1, 2, 0, 2, 1, 0) )
-        SET_SV_VL(2)
+        SET_SV_VL(3)
 
   mv a1, sp
   la sp, data;
@@ -44,6 +45,7 @@ RVTEST_CODE_BEGIN
 
         TEST_SV_IMM(a2, 1001) 
         TEST_SV_IMM(a3, 1002)
+        TEST_SV_IMM(a4, 1005)
 
   .option pop
 
@@ -57,7 +59,7 @@ RVTEST_CODE_END     # End of test code.
 data:
   .word 1001;
   .word 1002;
-  .word 0x01234567;
+  .word 1005;
 
 RVTEST_DATA_BEGIN