From: Jacob Lifshay Date: Fri, 12 Nov 2021 01:32:47 +0000 (-0800) Subject: change ternaryi to correct register fields X-Git-Tag: sv_maxu_works-initial~739 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=782d622d51388374db95c98b8a7ee7cfa8c3e30b;p=openpower-isa.git change ternaryi to correct register fields --- diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 1d0cd7ba..8da5faab 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -80,7 +80,6 @@ divduo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwuo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 -ternaryi,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 ffadds,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdivs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsubs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index e8184067..cdb0207e 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -31,6 +31,7 @@ isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 +ternaryi,,1P,EXTRA2,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 ffmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 ffmadds,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 ffnmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index 8fa5c11c..add3ff80 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,2 +1,2 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 ---------00-,ALU,OP_TERNARYI,RA,RB,CONST_TII,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternaryi,TI,,1,unofficial until submitted and approved/renumbered by the opf isa wg +--------00-,ALU,OP_TERNARYI,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternaryi,TI,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index cfb48698..2fa6feac 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -365,7 +365,7 @@ class DecodeC(Elaboratable): comb += reg.data.eq(self.dec.RC) comb += reg.ok.eq(1) with m.Case(In3Sel.RT): - # for TII-form ternary + # for TI-form ternary comb += reg.data.eq(self.dec.RT) comb += reg.ok.eq(1) diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 0ebf414d..87930703 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -478,8 +478,7 @@ class In3Sel(Enum): FRS = 3 FRC = 4 RC = 5 # for SVP64 bit-reverse LD/ST - CONST_TII = 6 # for ternaryi - XXX TODO: REMOVE THIS (from CSV, first) - RT = 7 # for ternary + RT = 6 # for ternary[i] @unique diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 3826f1e1..d62b5875 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -573,7 +573,12 @@ def process_csvs(): elif value == 'RM-1P-3S1D': res['Etype'] = 'EXTRA2' # RM EXTRA2 type - if insn_name == 'isel': + if regs == ['RA', 'RB', 'RT', 'RT', '', 'CR0']: + res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2 + res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 + res['2'] = 's:RB' # RT: Rsrc2_EXTRA2 + res['3'] = 's:RT' # RT: Rsrc3_EXTRA2 + elif insn_name == 'isel': res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2