From: lkcl <lkcl@web>
Date: Wed, 21 Sep 2022 13:31:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~342
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=782f16442a7057ae25cd7d79e42344eb564e6227;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 34fd99a63..f7d524584 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -265,9 +265,9 @@ of Simple-V.
 Simple-V is effectively a type of "Zero-Overhead Loop Control" to which
 an entire 24 bits are exclusively dedicated in a fully RISC-abstracted
 manner. Within those 24-bits there are no Scalar instructions, and
-no Vector instructions: there is only "Loop Control".
+no Vector instructions: there is *only* "Loop Control".
 
-This is why there are no actuak Vector operations in Simple-V: *all* suitable
+This is why there are no actual Vector operations in Simple-V: *all* suitable
 Scalar Operations are Vectorised or not at all.  This has some extremely
 important implications when considering adding new instructions, and
 especially when allocating the Opcode Space for them.