From: Eric Anholt <eric@anholt.net>
Date: Thu, 28 Dec 2017 23:42:14 +0000 (-0800)
Subject: broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7836c85919a289e806c4dbd3e7d080914049b130;p=mesa.git

broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.

Apparently the other funcs will have observable differences when early Z
is enabled.

Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
---

diff --git a/src/gallium/drivers/vc5/vc5_state.c b/src/gallium/drivers/vc5/vc5_state.c
index 35d5e1df509..0d6699ae57b 100644
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -165,8 +165,10 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
                           cso->depth.func == PIPE_FUNC_LEQUAL) &&
                          (!cso->stencil[0].enabled ||
                           (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
+                           cso->stencil[0].func == PIPE_FUNC_ALWAYS &&
                            (!cso->stencil[1].enabled ||
-                            cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
+                            (cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP &&
+                             cso->stencil[1].func == PIPE_FUNC_ALWAYS)))));
         }
 
         const struct pipe_stencil_state *front = &cso->stencil[0];