From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Thu, 1 Jun 2017 09:43:10 +0000 (+0200)
Subject: [ARC] Fix tst_movb pattern.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7841f13c8064c7d8f4eb13acd396bd0455e12c26;p=gcc.git

[ARC] Fix tst_movb pattern.

The tst_movb pattern is missing guarding when spitting.

gcc/
2017-06-01  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (tst_movb): Add guard when splitting.

testsuite/
2017-06-01  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/pr9001195952.c: New test.

From-SVN: r248783
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce7085b51ca..9ff24c97a3a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-06-01  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (tst_movb): Add guard when splitting.
+
 2017-06-01  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* config/arc/arc.c (arc_can_eliminate): Test against
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 501413854dd..9aa9cd7ae29 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -840,7 +840,7 @@
    (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,Rrq,c"))]
   "TARGET_NPS_BITOPS"
   "movb.f.cl %3,%1,%p2,%p2,%s2"
-  "reload_completed
+  "TARGET_NPS_BITOPS && reload_completed
    && (extract_constrain_insn_cached (insn), (which_alternative & ~1) != 6)"
   [(set (match_dup 0) (match_dup 4))])
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d8e3952003c..952bc9328ca 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2017-06-01  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* gcc.target/arc/pr9001195952.c: New test.
+
 2017-06-01  Tom de Vries  <tom@codesourcery.com>
 
 	* c-c++-common/pr43395.c: Add dg-require-effective-target label_values.
diff --git a/gcc/testsuite/gcc.target/arc/pr9001195952.c b/gcc/testsuite/gcc.target/arc/pr9001195952.c
new file mode 100755
index 00000000000..252438d8d78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/pr9001195952.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-mcpu=archs -Os -w -fpic" } */
+
+/* tst_movb split pattern is wrong for anything else than NPS
+   chip.  */
+__bswap_32___bsx() {
+  int a = __builtin_bswap32(__bswap_32___bsx);
+  if (a & 1048575)
+    zlog_warn();
+}