From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 17 Sep 2020 22:24:40 +0000 (-0700)
Subject: fix bug #492
X-Git-Tag: semi_working_ecp5~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=784c8b4561453cfeb585b24a16400223147902cd;p=soc.git

fix bug #492
---

diff --git a/src/soc/fu/div/fsm.py b/src/soc/fu/div/fsm.py
index 3af0928f..f5398b10 100644
--- a/src/soc/fu/div/fsm.py
+++ b/src/soc/fu/div/fsm.py
@@ -141,9 +141,8 @@ class FSMDivCoreStage(ControlBase):
     def __init__(self, pspec):
         super().__init__()
         self.pspec = pspec
-        # override p and n
-        self.p = FSMDivCorePrevControl(pspec)
-        self.n = FSMDivCoreNextControl(pspec)
+        self.p.data_i = CoreInputData(pspec)
+        self.n.data_o = CoreOutputData(pspec)
         self.saved_input_data = CoreInputData(pspec)
         self.empty = Signal(reset=1)
         self.saved_state = DivState(64, name="saved_state")