From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 5 May 2013 21:07:15 +0000 (+0200)
Subject: build.py: LOC clock generator components to limit breakage of the ISE shitware
X-Git-Tag: 24jan2021_ls180~2951
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=784e96bb8764ed212b530c159c1f66386fb28e3c;p=litex.git

build.py: LOC clock generator components to limit breakage of the ISE shitware
---

diff --git a/build.py b/build.py
index 73bd7720..a87c8a30 100755
--- a/build.py
+++ b/build.py
@@ -18,6 +18,8 @@ TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
 """, clk50=platform.lookup_request("clk50"))
 
 	platform.add_platform_command("""
+INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
+INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";