From: Tim Newsome <tim@sifive.com>
Date: Sat, 30 Apr 2016 22:24:38 +0000 (-0700)
Subject: Exceptions in Debug Mode, stay in Debug Mode.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=784fea2bbec803944eb923196c77d38427b3f554;p=riscv-isa-sim.git

Exceptions in Debug Mode, stay in Debug Mode.

Now things don't blow up when reading a non-existent CSR.
---

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 832ac49..b1fa8bd 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -20,14 +20,25 @@
 
         .global entry
         .global resume
+        .global exception
 
         # Automatically called when Debug Mode is first entered.
 entry:  j       _entry
         # Should be called by Debug RAM code that has finished execution and
         # wants to return to Debug Mode.
 resume:
+        j       _resume
+exception:
+        # Flip the LSB of the first word in Debug RAM so the debugger can know
+        # that we hit an exception.
+        lw      s1, (DEBUG_RAM)(zero)
+        xori    s1, s1, 1
+        sw      s1, (DEBUG_RAM)(zero)
+
+        # Fall through to resume.
+
+_resume:
         # Clear debug interrupt.
-clear_debint:
         csrr    s1, CSR_MHARTID
         sw      s1, CLEARDEBINT(zero)
         fence
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index 3ab78a1..f8aa2e0 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -1,17 +1,18 @@
 static const unsigned char debug_rom_raw[] = {
-  0x6f, 0x00, 0xc0, 0x04, 0xf3, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x90, 0x10,
-  0x0f, 0x00, 0xf0, 0x0f, 0xf3, 0x24, 0x00, 0xf1, 0x63, 0xc6, 0x04, 0x00,
-  0x83, 0x24, 0xc0, 0x43, 0x6f, 0x00, 0x80, 0x01, 0x93, 0x94, 0x14, 0x00,
-  0x63, 0xc6, 0x04, 0x00, 0x83, 0x34, 0x80, 0x43, 0x6f, 0x00, 0x80, 0x00,
-  0x13, 0x00, 0x00, 0x00, 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x84, 0x00,
-  0x63, 0x04, 0x04, 0x00, 0x6f, 0x00, 0x40, 0x05, 0x73, 0x24, 0x20, 0x79,
-  0x73, 0x00, 0x20, 0x30, 0x73, 0x10, 0x24, 0x79, 0x73, 0x24, 0x00, 0x79,
-  0x13, 0x74, 0x74, 0x00, 0x13, 0x04, 0xd4, 0xff, 0x63, 0x16, 0x04, 0x02,
-  0x73, 0x24, 0x00, 0xf1, 0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42,
-  0x67, 0x00, 0x00, 0x40, 0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00,
-  0x23, 0x3c, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40, 0x13, 0x00, 0x00, 0x00,
-  0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10,
-  0x73, 0x60, 0x04, 0x79, 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x04, 0x40,
-  0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfc
+  0x6f, 0x00, 0xc0, 0x05, 0x6f, 0x00, 0x00, 0x01, 0x83, 0x24, 0x00, 0xc0,
+  0x93, 0xc4, 0x14, 0x00, 0x23, 0x20, 0x90, 0xc0, 0xf3, 0x24, 0x50, 0xf1,
+  0x23, 0x2c, 0x90, 0xee, 0x0f, 0x00, 0xf0, 0x0f, 0xf3, 0x24, 0x00, 0xf1,
+  0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0xc3, 0x6f, 0x00, 0x80, 0x01,
+  0x93, 0x94, 0x14, 0x00, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x34, 0x80, 0xc3,
+  0x6f, 0x00, 0x80, 0x00, 0x13, 0x00, 0x00, 0x00, 0x73, 0x24, 0x00, 0x79,
+  0x13, 0x74, 0x84, 0x00, 0x63, 0x04, 0x04, 0x00, 0x6f, 0x00, 0x40, 0x05,
+  0x73, 0x24, 0x20, 0x79, 0x73, 0x00, 0x20, 0x10, 0x73, 0x10, 0x24, 0x79,
+  0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x74, 0x00, 0x13, 0x04, 0xd4, 0xff,
+  0x63, 0x16, 0x04, 0x02, 0x73, 0x24, 0x00, 0xf1, 0x63, 0x46, 0x04, 0x00,
+  0x23, 0x2e, 0x90, 0xc2, 0x67, 0x00, 0x00, 0xc0, 0x13, 0x14, 0x14, 0x00,
+  0x63, 0x46, 0x04, 0x00, 0x23, 0x3c, 0x90, 0xc2, 0x67, 0x00, 0x00, 0xc0,
+  0x13, 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0xc0, 0x73, 0x24, 0x50, 0xf1,
+  0x23, 0x20, 0x80, 0xf0, 0x73, 0x60, 0x04, 0x79, 0x73, 0x24, 0x00, 0x79,
+  0x13, 0x74, 0x04, 0x40, 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfc
 };
-static const unsigned int debug_rom_raw_len = 164;
+static const unsigned int debug_rom_raw_len = 180;
diff --git a/riscv/decode.h b/riscv/decode.h
index 3a8b3a4..067d426 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -239,6 +239,7 @@ private:
 #define DEBUG_START             0x100
 #define DEBUG_ROM_START         0x800
 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
+#define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
 #define DEBUG_ROM_END           (DEBUG_ROM_START + debug_rom_raw_len)
 #define DEBUG_RAM_START         0x400
 #define DEBUG_RAM_SIZE          64
diff --git a/riscv/execute.cc b/riscv/execute.cc
index a1c2229..f67843e 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -61,9 +61,9 @@ void processor_t::step(size_t n)
   }
 
   if (state.dcsr.cause != DCSR_CAUSE_NONE) {
-    // In Debug Mode, just do 10 steps at a time. Otherwise we're going to be
+    // In Debug Mode, just do 11 steps at a time. Otherwise we're going to be
     // spinning the rest of the time anyway.
-    n = std::min(n, (size_t) 10);
+    n = std::min(n, (size_t) 11);
   }
 
   while (n > 0) {
diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index c254ab0..f2dd6af 100644
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -295,6 +295,10 @@ class register_read_op_t : public operation_t
         gs.write_debug_ram(0, csrr(S0, reg - REG_CSR0));
         gs.write_debug_ram(1, sd(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
         gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
+        // If we hit an exception reading the CSR, we'll end up returning ~0 as
+        // the register's value, which is what we want. (Right?)
+        gs.write_debug_ram(4, 0xffffffff);
+        gs.write_debug_ram(5, 0xffffffff);
       } else {
         gs.send_packet("E02");
         return true;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index d937f2e..7f3ba42 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -236,7 +236,11 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     set_csr(CSR_MSTATUS, s);
     set_privilege(PRV_S);
   } else {
-    state.pc = state.mtvec;
+    if (state.dcsr.cause) {
+      state.pc = DEBUG_ROM_EXCEPTION;
+    } else {
+      state.pc = state.mtvec;
+    }
     state.mcause = t.cause();
     state.mepc = epc;
     if (t.has_badaddr())