From: Icenowy Zheng <icenowy@aosc.io>
Date: Tue, 18 Dec 2018 06:38:44 +0000 (+0800)
Subject: anlogic: fix dbits of Anlogic Eagle DRAM16X4
X-Git-Tag: yosys-0.9~348^2~3^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7854d5ba217788bb66881237feac8ba2748758b9;p=yosys.git

anlogic: fix dbits of Anlogic Eagle DRAM16X4

The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.

Fix the dbits number in the RAM configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---

diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
index 2bff14a03..eb94775ae 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/drams.txt
@@ -1,7 +1,7 @@
 bram $__ANLOGIC_DRAM16X4
   init 0
   abits 4
-  dbits 2
+  dbits 4
   groups 2
   ports  1 1
   wrmode 0 1