From: lkcl <lkcl@web>
Date: Sun, 24 Jul 2022 15:16:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1049
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7872f27a9478f88c6c2988028fd939d1d707c384;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index bbcc3ced9..d1fa3f426 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -216,8 +216,8 @@ There are **no** Vector Instructions and consequently **no further
 opcode space is required**.  Even though they are currently
 placed in the EXT022 Sandbox, the "Management" instructions
 (setvl, svstep, svremap, svshape, svindex) are designed to fit
-cleanly into EXT019 (like `addpcis`) or other 5/6-bit Minor
-XO area that has space for Rc=1.
+cleanly into EXT019 (exactly like `addpcis`) or other 5/6-bit Minor
+XO area (bits 25-31) that has space for Rc=1.
 
 That said: for the target workloads for which Scalable Vectors are typically
 used, the Scalar ISA on which those workloads critically rely