From: Uros Bizjak Date: Wed, 18 May 2016 19:15:22 +0000 (+0200) Subject: re PR target/71145 (Alpha: Error: No lda !gpdisp!278 was found) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78885314088bb56f3c4fa60e4f0b6dfd987b3691;p=gcc.git re PR target/71145 (Alpha: Error: No lda !gpdisp!278 was found) PR target/71145 * config/alpha/alpha.md (trap): Add (use (reg:DI 29)). (*exception_receiver_1): Return "#" for TARGET_EXPLICIT_RELOCS. From-SVN: r236423 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bb7855e8d06..4d261f7872d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-05-18 Uros Bizjak + + PR target/71145 + * config/alpha/alpha.md (trap): Add (use (reg:DI 29)). + (*exception_receiver_1): Return "#" for TARGET_EXPLICIT_RELOCS. + 2016-05-18 Martin Jambor PR ipa/69708 @@ -61,8 +67,7 @@ loaded via XXSPLTIB. (all_ones_constant): New predicate for vector constant with all 1's set. - (splat_input_operand): Add support for ISA 3.0 word splat - operations. + (splat_input_operand): Add support for ISA 3.0 word splat operations. * config/rs6000/rs6000.c (xxspltib_constant_p): New function to return if a constant can be loaded with the ISA 3.0 XXSPLTIB instruction and possibly with a sign extension. @@ -106,7 +111,7 @@ (vsx_movti_64bit): Fold movti into normal vector moves. (vsx_movti_32bit): Likewise. (vsx_splat_, V4SI/V4SF modes): Add support for ISA 3.0 word - spat instructions. + splat instructions. (vsx_splat_v4si_internal): Likewise. (vsx_splat_v4sf_internal): Likewise. (vector fusion peepholes): Use VSX_M instead of VSX_M2. @@ -219,7 +224,7 @@ 2016-05-18 Kirill Yukhin - * gcc/config/i386/sse.md (define_insn "*andnot3"): Extend static + * gcc/config/i386/sse.md (define_insn "*andnot3"): Extend static array to 128 chars. (define_insn "*andnottf3"): Ditto. (define_insn "*3"/any_logic): Ditto. @@ -235,7 +240,7 @@ 2016-05-18 Petr Murzin Kirill Yukhin - * config/i386/sse.md (define_insn "srcp14"): Use proper operand + * config/i386/sse.md (define_insn "srcp14"): Use proper operand modifiers. (define_insn "rsqrt14"): Ditto. (define_insn "avx512dq_cvtps2qqv2di"): Ditto. @@ -288,7 +293,8 @@ 2016-05-17 Kugan Vivekanandarajah - * config/aarch64/aarch64.c (all_extensions): Removed unused static variable. + * config/aarch64/aarch64.c (all_extensions): Removed unused + static variable. 2016-05-17 Nathan Sidwell @@ -363,8 +369,8 @@ 2016-05-17 Jiong Wang - * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_to_128df): Extend to - all supported modes. Rename to "*aarch64_mul3_elt_from_dup". + * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_to_128df): Extend + to all supported modes. Rename to "*aarch64_mul3_elt_from_dup". 2016-05-17 Jiong Wang @@ -381,7 +387,7 @@ 2016-05-17 Gerald Pfeifer * wide-int.h: Change fixed_wide_int_storage from class to struct. - + 2016-05-17 Richard Biener PR tree-optimization/71132 @@ -422,7 +428,7 @@ 2016-05-16 Wilco Dijkstra - * doc/invoke.texi (AArch64 Options): Various updates. + * doc/invoke.texi (AArch64 Options): Various updates. 2016-05-16 Jan Hubicka @@ -717,11 +723,11 @@ 2016-05-13 Ramana Radhakrishnan - PR target/53440 - * config/arm/arm.c (arm32_output_mi_thunk): New. - (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk. Rework - to split Thumb1 vs TARGET_32BIT functionality. - (arm_thumb1_mi_thunk): New. + PR target/53440 + * config/arm/arm.c (arm32_output_mi_thunk): New. + (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk. Rework + to split Thumb1 vs TARGET_32BIT functionality. + (arm_thumb1_mi_thunk): New. 2016-05-13 Ramana Radhakrishnan @@ -1258,9 +1264,9 @@ 2016-05-04 Aaron Sawdey - * config/rs6000/rs6000.c (rs6000_reassociation_width): Add - function for TARGET_SCHED_REASSOCIATION_WIDTH to enable - parallel reassociation for power8 and forward. + * config/rs6000/rs6000.c (rs6000_reassociation_width): Add + function for TARGET_SCHED_REASSOCIATION_WIDTH to enable + parallel reassociation for power8 and forward. 2016-05-09 Uros Bizjak diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 932608b0fe2..3e4594bf4c6 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -3738,7 +3738,8 @@ ;; BUGCHK is documented common to OSF/1 and VMS PALcode. (define_insn "trap" - [(trap_if (const_int 1) (const_int 0))] + [(trap_if (const_int 1) (const_int 0)) + (use (reg:DI 29))] "" "call_pal 0x81" [(set_attr "type" "callpal")]) @@ -5157,7 +5158,7 @@ "TARGET_ABI_OSF" { if (TARGET_EXPLICIT_RELOCS) - return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"; + return "#"; else return "ldgp $29,0($26)"; }