From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 Jul 2022 20:42:08 +0000 (+0100)
Subject: move inputs in ISACaller into get_input()
X-Git-Tag: sv_maxu_works-initial~240
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=788f9699e90c9f5311cdfa8e0994b0a28490833f;p=openpower-isa.git

move inputs in ISACaller into get_input()
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index e592d84d..4b9f1a59 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1331,30 +1331,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # main input registers (RT, RA ...)
         inputs = []
         for name in input_names:
-            # using PowerDecoder2, first, find the decoder index.
-            # (mapping name RA RB RC RS to in1, in2, in3)
-            regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
-            if regnum is None:
-                # doing this is not part of svp64, it's because output
-                # registers, to be modified, need to be in the namespace.
-                regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
-            if regnum is None:
-                regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2,
-                                                                 name)
-
-            # in case getting the register number is needed, _RA, _RB
-            regname = "_" + name
-            self.namespace[regname] = regnum
-            if not self.is_svp64_mode or not pred_src_zero:
-                log('reading reg %s %s' % (name, str(regnum)), is_vec)
-                if name in fregs:
-                    reg_val = SelectableInt(self.fpr(regnum))
-                elif name is not None:
-                    reg_val = SelectableInt(self.gpr(regnum))
-            else:
-                log('zero input reg %s %s' % (name, str(regnum)), is_vec)
-                reg_val = 0
-            inputs.append(reg_val)
+            regval = (yield from self.get_input(name))
+            inputs.append(regval)
+
         # arrrrgh, awful hack, to get _RT into namespace
         if ins_name in ['setvl', 'svstep']:
             regname = "_RT"
@@ -1530,6 +1509,31 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         if nia_update:
             self.update_pc_next()
 
+    def get_input(self, name):
+        # using PowerDecoder2, first, find the decoder index.
+        # (mapping name RA RB RC RS to in1, in2, in3)
+        regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
+        if regnum is None:
+            # doing this is not part of svp64, it's because output
+            # registers, to be modified, need to be in the namespace.
+            regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
+        if regnum is None:
+            regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2, name)
+
+        # in case getting the register number is needed, _RA, _RB
+        regname = "_" + name
+        self.namespace[regname] = regnum
+        if not self.is_svp64_mode or not self.pred_src_zero:
+            log('reading reg %s %s' % (name, str(regnum)), is_vec)
+            if name in fregs:
+                reg_val = SelectableInt(self.fpr(regnum))
+            elif name is not None:
+                reg_val = SelectableInt(self.gpr(regnum))
+        else:
+            log('zero input reg %s %s' % (name, str(regnum)), is_vec)
+            reg_val = 0
+        return reg_val
+
     def remap_debug(self, remaps):
         # just some convenient debug info
         for i in range(4):