From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 2 Aug 2019 05:30:10 +0000 (-0700)
Subject: Add TODO
X-Git-Tag: working-ls180~1161^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=789585a7445f8d63d9a251a9781434bc60d7f30c;p=yosys.git

Add TODO
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index df14f8f7e..f15aded84 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -736,6 +736,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			}
 		}
 
+		// TODO: Move this optimisation into parse_xaiger, so that we
+		//       can get save on the "clean" call at the end of this function
 		for (auto &it : bit_users)
 			if (bit_drivers.count(it.first))
 				for (auto driver_cell : bit_drivers.at(it.first))