From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 02:59:24 +0000 (-0700)
Subject: Another typo
X-Git-Tag: working-ls180~881^2^2~268
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7899a06ed64c55e8d804ef2970ad983e3d112013;p=yosys.git

Another typo
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 91cfbc4c4..6f9011ef1 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -94,7 +94,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
+  \$__ABC_FDPE #(
     .INIT(|0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),