From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 18:08:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2531
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78b645db5b13d96d80d6ae99b253b5599eafbe16;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 4d7b7b46a..8fb2a629c 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -1076,6 +1076,11 @@ RT0 to RT2 are stored:
      r4  RT1.hi    RT2.hi
      r5  unchanged unchanged
 
+Note that all of the LO halves start from r1, but that the HI halves
+start from half-way into r3. The reason is that with MAXVL bring
+5 and elwidth being 32, this is the 5th element
+offset (in 32 bit quantities) counting from r1.
+
 Additional DRAFT Scalar instructions in 3-in 2-out form
 with an implicit 2nd destination: