From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Tue, 26 Oct 2010 09:20:44 +0000 (-0700)
Subject: [pk,sim,xcc] get rid of at register, introduce tp register
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78bc7d988509ef8364cb39f96d29f8a615bb10f1;p=riscv-isa-sim.git

[pk,sim,xcc] get rid of at register, introduce tp register
---

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 1d6b4d1..de3c19d 100644
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -11,8 +11,7 @@ switch(insn.rtype.rs2)
     break;
 
   case 29:
-    val = tid;
-    break;
+    throw trap_illegal_instruction;
 
   default:
     val = -1;
diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h
index ba55899..df56ecd 100644
--- a/riscv/insns/mtcr.h
+++ b/riscv/insns/mtcr.h
@@ -5,6 +5,5 @@ switch(insn.rtype.rs2)
     break;
 
   case 29:
-    tid = RS1;
-    break;
+    throw trap_illegal_instruction;
 }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index a889f75..684f95d 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -19,7 +19,6 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   epc = 0;
   badvaddr = 0;
   cause = 0;
-  tid = 0;
   pcr_k0 = 0;
   pcr_k1 = 0;
   tohost = 0;
diff --git a/riscv/processor.h b/riscv/processor.h
index c1e4740..9ccfbb4 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -39,7 +39,6 @@ private:
   uint32_t interrupts_pending;
 
   // unprivileged control registers
-  uint32_t tid;
   uint32_t fsr;
 
   // 32-bit or 64-bit mode (redundant with sr)