From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 16 Dec 2019 22:35:35 +0000 (-0800)
Subject: Revert "write_xaiger: use sigmap bits more consistently"
X-Git-Tag: working-ls180~881^2^2~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78c0246d4abbd290289ed55a0008968293119446;p=yosys.git

Revert "write_xaiger: use sigmap bits more consistently"

This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index cff3183c1..c080cca4d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -294,7 +294,7 @@ struct XAigerWriter
 							output_bits.insert(b);
 
 							if (!cell_known)
-								inout_bits.insert(I);
+								inout_bits.insert(b);
 						}
 					}
 				}
@@ -315,7 +315,7 @@ struct XAigerWriter
 						SigBit O = sigmap(b);
 						if (O != b)
 							alias_map[O] = b;
-						input_bits.insert(O);
+						input_bits.insert(b);
 
 						if (arrival)
 							arrival_times[b] = arrival;
@@ -542,8 +542,9 @@ struct XAigerWriter
 				undriven_bits.erase(bit);
 			}
 
-		// For inout ports, or keep-ed wires, which end up being both a PI and a
-		// a PO then replace the PO with a new wire with the $inout.out suffix
+		// For inout ports, or keep-ed wires, then create a new wire with an
+		// $inout.out suffix, make it a PO driven by the existing inout, and
+		// inherit existing inout's drivers
 		for (auto bit : inout_bits) {
 			RTLIL::Wire *wire = bit.wire;
 			RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());