From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 10 Jun 2021 10:50:44 +0000 (+0100)
Subject: move VCC/VSS inward on NORTH
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78d460bdb156e73e5ee90b7a75df1f9536951b9a;p=pinmux.git

move VCC/VSS inward on NORTH
---

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index ca3401e..763621f 100644
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -77,7 +77,7 @@ def pinspec():
     ps.sdram2("", ('W', 4), 0, 0, 12)
     ps.sdram1("", ('W', 16), 0, 21, 9)
     ps.uart("0", ('W', 22), 0)
-    ps.jtag("", ('W', 24), 0, 0, 4)
+    ps.mspi("0", ('W', 24), 0)
     ps.vss("I", ('W', 28), 0, 3, 1)
     ps.vdd("I", ('W', 29), 0, 3, 1)
     ps.vss("E", ('W', 30), 0, 3, 1)
@@ -88,26 +88,27 @@ def pinspec():
     ps.vdd("I", ('E', 2), 0, 4, 1)
     ps.vss("I", ('E', 3), 0, 4, 1)
     ps.sys("", ('E', 4), 0, 5, 1) # analog VCO out in right top
-    ps.mspi("0", ('E', 5), 0)
-    ps.gpio("", ('E', 9), 0, 0, 16)
+    ps.gpio("", ('E', 5), 0, 0, 8) # split GPIO 8-8
+    ps.jtag("", ('E', 13), 0, 0, 4)
+    ps.gpio("", ('E', 17), 0, 8, 8) # the other 8 GPIO
     ps.eint("", ('E', 25), 0, 0, 3)
     ps.vss("I", ('E', 28), 0, 5, 1)
     ps.vdd("I", ('E', 29), 0, 5, 1)
     ps.vss("I", ('E', 30), 0, 5, 1)
     ps.vdd("I", ('E', 31), 0, 5, 1)
 
-    ps.vss("E", ('N', 0), 0, 6, 1)
-    ps.vdd("E", ('N', 1), 0, 6, 1)
-    ps.vdd("I", ('N', 2), 0, 6, 1)
-    ps.vss("I", ('N', 3), 0, 6, 1)
+    ps.vss("E", ('N', 6), 0, 6, 1)
+    ps.vdd("E", ('N', 7), 0, 6, 1)
+    ps.vdd("I", ('N', 8), 0, 6, 1)
+    ps.vss("I", ('N', 9), 0, 6, 1)
     #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
     #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
     #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
-    ps.sys("", ('N', 23), 0, 0, 5) # all but analog out in top right
-    ps.vss("I", ('N', 28), 0, 7, 1)
-    ps.vdd("I", ('N', 29), 0, 7, 1)
-    ps.vss("I", ('N', 30), 0, 7, 1)
-    ps.vdd("I", ('N', 31), 0, 7, 1)
+    ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
+    ps.vss("I", ('N', 22), 0, 7, 1)
+    ps.vdd("I", ('N', 23), 0, 7, 1)
+    ps.vss("I", ('N', 24), 0, 7, 1)
+    ps.vdd("I", ('N', 25), 0, 7, 1)
 
     #ps.mquadspi("1", ('S', 0), 0)